Universal Remote Control R7 - SPECS SHEET Manuel d'utilisateur télécharger pdf (Page 4)

ADP5586 Data Sheet

Rev. 0 | Page 4 of 44

C TIMING SPECIFICATIONS

Table 2.

Parameter Description Min Max Unit

C TIMING SPECIFICATIONS

Delay from UVLO/RST Inactive to I

C Access

60 μs

SCL

SCL clock frequency 0 1000 kHz

HIGH

SCL high time 0.26 μs

LOW

SCL low time 0.5 μs

SU; DAT

Data setup time 50 ns

HD; DAT

Data hold time 0 μs

SU; STA

Setup time for repeated start 0.26 μs

HD; STA

Hold time for start/repeated start 0.26 μs

BUF

Bus free time for stop and start conditions 0.5 μs

SU; STO

Setup time for stop condition 0.26 μs

VD; DAT

Data valid time 0.45 μs

VD; ACK

Data valid acknowledge 0.45 μs

Rise time for SCL and SDA 120 ns

Fall time for SCL and SDA 120 ns

Pulse width of suppressed spike 0 50 ns

Capacitive load for each bus line 550 pF

is the total capacitance of one bus line in picofarads (pF).

Timing Diagram

SDA

SCL

SDA

SCL

Sr PS

FIRST CLOCK CYCLE

NINTH CLOCK

SCL

70%

30%

70%

30%

70%

30%

70%

30%

70%

30%

70%

30%

70%

30%

HIGH

VD; DAT

SU; DAT

SU; STA

HD; DAT

HD; STA

VD; ACK

SU; STO

BUF

LOW

HD; STA

= 0.3V × VDD

= 0.7V × VDD

11148-002

Figure 2. I

C Interface Timing Diagram

1 2 3 4 5 6 7 8 9 ... 43 44

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